The reverse engineering of an integrated circuit consists in analyzing the integrated circuit in order to determine its internal structure and its operation with a view for example to copying and to re-fabricating.
A critical step in a process of reverse engineering is the recognition of the standard cells and of the various components by means of a pattern matching technique for the purpose of determining the list of interconnections and of components (or ‘netlist’) and potentially of reconstructing the hierarchy of the integrated circuit.
More precisely, once a cell or a component has been identified, all the identical instances of this cell or of this component within the integrated circuit are sought using the pattern matching technique.
Current solutions for attempting to counteract such a search are based on the error tolerance of such a pattern matching technique. More precisely, they are based on specific designs of cells providing very similar layouts for cells having different functionalities.
However, such solutions require the implementation of input and output stages with a conventional CMOS structure, hence prohibiting an output stage being equipped with a specific non-CMOS component with a view, for example, to carrying out a correct characterization over time, or else to obtaining a high input capacitance for the input stage.